This application claims priority and benefit of Korean Patent Application No. 2001-0085924, filed on Dec. 27, 2001, the contents of which are incorporated herein by reference in their entirety.
This invention relates to semiconductor chip packaging technology, and more particularly to a stack chip package of high I/O pins and a lead frame suitable for such stack chip package.
Semiconductor integrated circuit (IC) chips may be assembled into package devices for mounting on circuit boards. Conventionally, the package device may use a media for electrical interconnection and physical support of the chip to the circuit board. A lead frame is a common media for such purposes.
In order to increase a density of packaged semiconductor devices, semiconductor IC chips may be mounted on both sides of a lead frame. Conventional packaged devices may employ a lead frame that comprises a die region and a number of conductive leads. The semiconductor IC chips may be physically bonded to the die region by an adhesive and may be electrically interconnected to the conductive leads by metal bond wires. The IC chips and bond wires may then be encapsulated and molded within an epoxy resin to form a package body to protect the chips from an external environment. Outer portions of the leads, i.e., the outer leads that protrude from the package body, may be bent or shaped to assist mounting to a circuit board.
Further developments in chip stacking technology have led to the use of two lead frames of central pad LOC (Lead-On-Chip) type for enhancing the mounting density of memory devices such as DRAMs. This package is a kind of DDP (Dual Die Package) and since a lead frame is used, a multi-wiring pattern structure cannot be used. Thus, more input and output terminals may be required than what might otherwise be available with tape or PCB (Printed Circuit Board) type packages. Additionally, design limitations may exist in implementing these types of devices for high bit structures.
Addressing such problems, some manufacturers have tried to modify the conventional package structures so that a PCB or tape style conductive wiring pattern may be attached to a lead frame. However, such modified structures have not been widely accepted in the industry because of difficulties associated with manufacturing these lead frames, increased cost and other technical limitations.
For instance, X32 structure devices such as 2MX32 and 4MX32 SRAMs may be produced by designing X32 chips incorporated with TSOP (86 pin I/O) or FBGA technology. Some manufacturers may produce X32 MCP package device by using two X16 chips and a substrate routing technique with PCB or tape. However, there have been no producers of a high-bit device (e.g., X32 device) incorporating two X16 chips with a lead frame.
An exemplary embodiment of the present invention may increase capacity of high bit memory devices by using a simple lead frame process absent additional PCB or tape.
Further exemplary embodiments may provide for methods of forming stack package devices of high capacity and multi-bit structures using conventional tools and may avoid the need for new equipment investments.
According to one embodiment of the present invention, a stack semiconductor chip package may comprise a lead frame coupled to first and second stacked chips. The lead frame may comprise first and second lead groups for coupling the respective first and second chips to external connection terminals. Each of the first and second chips may comprise their own common and independent electrode pads. Likewise, each of the first and second lead groups may comprise common and independent leads. The common leads and the common electrode pads may be associated with address and control signals. The independent leads and the independent electrode pads, on the other hand, may be associated with data signals. The common leads of the first lead group may be interconnected to respective common leads of the second lead group for propagation of same associated address or control signals. The commonly interconnected leads may be connected through respective ones of the external connection terminals for routing of their address and control signals. The independent leads of the first lead group and the independent leads of the second lead group may be connected separately and independently to different terminals of the plurality of external connection terminals. The first and second chips may be disposed back-to-back and in symmetrical relationship to each other when viewed with respect to the common leads.
In a particular exemplary embodiment of the present invention, two memory devices may be incorporated together with two LOC type lead frames. This stack package may assist increased memory capacity and bit structures. For example, two X16 memory devices may be stacked to provide a X32 package device. Each of the semiconductor chips may have common electrode pads of a mirrored relationship to each other. Additionally, at least some of the electrode pads of upper and lower chips of the stack may comprise sequential signal assignments of the same order within the package. In one embodiment, the mirrored arrangements of pads may be implemented by using alternative metal processes during fabrication of the electrode pads of the lower chip relative to the upper chip. In another embodiment, a wire bonding option may be used to provide for the arrangements of electrode pad structures for the upper and lower chips. In accordance with a further embodiment, the plurality of semiconductor chips within the stack are of the same function. In another embodiment, the chips comprise devices of different function.
According to another embodiment of the present invention, a stack semiconductor chip package may comprise a plurality of stacked semiconductor chips and a lead frame. The lead frame may comprise a plurality of lead groups that correspond to respective chips of the plurality of chips. A plurality of external connection terminals may electrically interconnect the chips to an external device. In a particular embodiment, the semiconductor chips are of central pad type with electrode pads disposed at the central regions of the active surfaces of the chips. The electrode pads may include common and independent electrode pads. The lead groups overlie and may be attached to the active surfaces of the respective chips. Each of the lead groups may comprise common and independent leads. The common leads and the common electrode pads may route address and control signals to and from the first and second semiconductor chips. The independent leads and the independent electrode pads may route data input and output signals to and from the first and second semiconductor chips. The respective common leads of the plurality of lead groups may be interconnected to each other and to associated identical external connection terminals of the plurality of external connection terminals. In a further aspect, the first and second semiconductor chips may be disposed back-to-back and in symmetrical relationship to each other relative to the common leads.
Exemplary embodiments of the present invention may enable formation of high-bit IC devices using tools of traditional lead frame technology.
These and other features and advantages will be more clearly understood from the following detailed description taken together with the accompanying drawings. It is important to point out that the illustrations may not necessarily be drawn to scale, and that there may be other embodiments of this invention which are not specifically illustrated.